The present invention concerns the management of the flows or transfers of information within a hierarchy of memories, and particularly between two contiguous levels of memories, the faster one of which is used by instruction processors, the one or ones of the lower speed levels being managed only by circuits which can be called (control processors), such circuits existing at a higher speed level in addition to, or in combination with, instruction processors.
Hierarchies of memories are now being generally used in the information processing equipments, because they make it possible to dispose of a memory space as large as possible, for example, currently now of about a billion octets, without the costs becoming prohibitive, as in this hierarchy the various technologies participate in reverse proportion to their own costs. As a result, one can introduce--or at least hope to introduce--in the fastest memories, those which are normally associated with instruction processors, the most useful information with an apparent average access time of the order of the time of the cycle of the fastest part of the hierarchy, for a total capacity equal to that of the lowest speed level.
The management of the levels of such a hierarchy of memories poses, inter alia, the problem of the coherence of information flows between different levels of this hierarchy. Such problem exists each time a level contains several blocks with autonomous control, which hold a dialog with the same block of a lower speed level during the processing of data which can be modified at the higher speed level, in the course of implementation of a task which has exclusive or non-exclusive access to modifiable information. Incoherence can occur, when copies of the same original information may exist and be modified in several independent blocks of this higher speed level. One refers here by the term "block" to any part of memory or any memory unit which, in a level, is managed in an autonomous way by a local control processor, which may be confused, at least at the highest speed level, with one or several of the instruction processors which exist there.
In accordance with current terminology, one will designate by a page the smallest quantity of information existing at a level of the hierarchy which can be exchanged with the contiguous lower speed level, while this page can be divided into fragments for exchanges with the contiguous higher speed level. Usually, the size of the page is a power of two, and it is convenient for the exchanges that the pages of a level are of a size multiple of those of the contiguous higher speed level.
A table or repertory of status word is most often associated with the control processor of each block such a repertory of status words comprises as many entries as there are pages in the block, or even as many entries as fragments of pages. Each word of the repertory includes at least one information address and status bits concerning the said information.
In French patent specification 75 12 014 filed 17 Apr. 1975 for "Method and Means for a Coherent Management of Information in a Hierarchy of Memories" (Invention by Paul FEAUTRIER), the assignee of the present application described a method which is characterized in a general manner by the fact that each control processor of a block of the higher speed level, cooperating with a determined plurality of blocks of the higher speed level, each of them associated with a control processor and/or instruction processor, memorizes for each page of the block, in the entry of its repertory corresponding to that page, the read-out operations directed to--and write-in operations as well as operations signalling ejection which are coming from--the highest speed level, and by the fact that each time a request is made to read a fragment of a page of the block, the control processor of this block consults the contents memorized in the given entry of the repertory, in order to determine whether this request can be satisfied immediately, or whether the blocks of the higher speed level, which previously have received fragments of the same page, should first have these copies eliminated from them. Such an elimination opertaion may be called a "purge".
According to a special method of implementation of the method, each page entry, of the repertory of the lower speed level is subdivided into as many places of memorization of these operations as there are blocks at the higher speed level. If necessary, each of such places can be in turn subdivided into as many places of memorization as there are fragments on the page of the block of the lower speed level.
When the items of information are provided, at least for each page of the block the lower speed level, with a marker index indicating whether the information is modifiable or not at the higher speed level, the consultation of the table by the control processor of the lower speed level also applies to that index. When the information is thus determined as being non-modifiable, the request for reading is complied with immediately, without a priorly executed purging operation.
The modalities of the use of this method have revealed in actual practice certain counterparts which contribute to the slowdown of the exchanges between the different levels, and especially between the fastest level, usually managed by instruction processors carrying out each of the programs of tasks the profession of which requires numerous exchanges between their autonomous blocks and that of the lower speed level, which serves them and is managed by a simple control processor. It is plainly understandable that full coherence must be most strictly observed between these two levels.
In the said French patent, the management of the exchanges is in fact assumed entirely at the lower speed level. The memorization and the accounting of the exchange operations is in charge of the repertory of the status words, or "table", which is associated with the autonomous control processor of a block of the lower speed level. The management of the exchanges is thus depending on the access delays of this lower speed level. The decision of purge operations is taken at this lower speed level and, accordingly, each order of purge carried out in this way does not discriminate, at the higher speed level, between the fragments of the page which it orders to be recopied in the block of the higher speed level. This means "repatriation" of as well the information which cannot be modified, for example information concerning the programs, as well as information which can be modified were not, and even modifiable information which had been modified but which belongs only to the task in progress in the processor associated with the block concerned of the higher speed level. Consequently there is a loss of time and therefore a decrease of efficiency, which is often greater than desirable, because each "repatriation" requires a time for access which is the one of the block of the lower speed level. Posting in the table an index specifying that the information is determined to be modifiable or non-modifiable at the higher speed level, reduces the number of purging orders, but it does not reduce the duration of execution of each other, and such reduction is hindered in some way by the fact that such index can be applied only to the entire content of a page of the block of the lower speed level, in order not to unduly increase the capacity of the table associated with each control processor of the lower speed level. Even if this index was applied to each fragment and in order to make sure that such indexing could be validly applied, it would be necessary that the decision be made at the higher speed level during the transfer of the fragment, and consequently the decision would have to be transferred back to the lower speed level for memorization, which would clearly result in a loss of time.